1. Field of the Invention
The present invention relates generally to achieving higher density of non-volatile memories, and more specifically to techniques for effectively reducing cell areas of non-volatile memories, such as flash memories, using a so-called "contactless" approach.
2. Description of the Related Art
Non-volatile memories use a variety of memory cell designs. One type of non-volatile memory cells uses an electrically isolated floating gate to trap charge, and this type of memory cell is referred to as a flash memory. Flash memory is a new variation of a programmable non-volatile memory, which is gaining favor because they can be erased and programmed (or reprogrammed) faster than the existing EPROMs (erasable programmable read-only memories), and because they use a simpler storage cell, thereby allowing more memory cells on a single chip.
Prior to turning to the present invention, it is deemed preferable to describe, with reference to FIGS. 1 to 4, a conventional flash memory that may be relevant to the present invention.
FIG. 1 is a circuit diagram schematically showing part of a flash memory cell block before metal lines for interconnecting memory cell blocks are not yet provided. As shown in FIG. 1, the flash memory cell block, denoted by numeral 10, comprises two identical memory sections 12A and 12B that are arranged in a mirror image relationship with respect to a phantom line 14. Thus, only the memory section 12B will be described for the sake of simplifying the disclosure. The memory section 12B comprises a plurality of pairs of floating gate transistors 16aa-16ab, 16ba-16bb, . . . , 16na-16nb each provided in the row direction.
Each pair of the floating gate transistors 16 is formed so as to assume a drain-source-drain configuration in this particular case, wherein a single source diffusion is shared by two columns of floating gate transistors. Five elongated buried diffusion regions 18a-18e are formed on a semiconductor substrate (not shown) in parallel in the column direction. More specifically, each of the diffused regions 18a and 18e is used to form drain regions as well as local bit lines, while each of the diffused regions 18b and 18d is used to form a channel between drain and source of each floating gate transistor. On the other hand, the elongated diffusion region 18c is utilized to form the source areas of the memory cells and also a source connecting line. The elongated diffusion regions 18a-18e are buried one over which metal lines are provided as mentioned later.
Further, a plurality of word lines Wa-Wn are formed in a manner that is normal to each of the elongated diffusion regions 18a-18e (viz., in the row direction), and are coupled to the gate electrodes of the corresponding memory cell transistors 16aa, 16ab, . . . , 16nb. Still further, column select transistors 20a and 20b are provided whose on/off operations are controlled by a column select signal appearing on a column select line 22. Two bit line contacts 24a and 24b are respectively provided for coupling the bit lines 18a and 18e to corresponding main (or global) bit lines as discussed later. Some components in the other (viz., upper) section 12A are denoted by the same reference numerals (notations) used with the corresponding ones in the lower section 12A plus a prime.
FIG. 2 is a diagram schematically showing layout of a plurality of memory cell blocks in the vicinity of the bit line contacts 24a and 24b. The arrangement shown in FIG. 2 is readily understood when referring back to the circuitry of FIG. 1 and thus, further descriptions of the layout of FIG. 2 will not be given for brevity.
FIG. 3 is a circuit diagram showing two main bit lines 30a and 30b and a main source line 32, which are added to the circuit shown in FIG. 1. Although it is not clear from FIG. 3, the main bit lines 30a and 30b are provided over the buried diffusion regions 18a and 18e by way of a suitable insulation layer (not shown). The main bit lines 30a and 30b are respectively coupled to the local (viz., buried) bit lines 18a and 18b via the column select transistors 20a and 20b. On the other hand, the main source line 32 is also provided over the buried local source line 18c.
FIG. 4 is a diagram schematically showing layout of a plurality of memory cell blocks whose circuitry has been shown in FIG. 3. It is understood that the main bit lines 30a and 30b and the main source line 32 are respectively provided onto the buried diffusion regions 18a, 18c, and 18e by way of a suitable insulator (not shown).
A so-called "contactless" array is the array of memory cells which are interconnected via buried diffusion in the column direction, and the array has one contact every predetermined number of rows. Thus, elimination of contacts between the buried and main bit lines results in a cell area shrink. The above-mentioned drain-source-drain configuration of the contactless EPROM cell is disclosed by U.S. Pat. No. 5,526,307 to Yiu et al., U.S. Pat. No. 5,691,938 to Yiu et al., or Japanese Laid-open Patent Application No. 6-283721.
As is known in the art, there are typically two ways for programming and erase operations. That is, one way is to use channel hot electron injection for programming and Fowler-Nordheim tunneling for erase, while the other way utilizes Fowler-Nordheim tunneling for both programming and erase. In either case, electrons are extracted by applying a voltage to the source or drain. Thus, in order not to disturb the memory cells with which no programming or erase is implemented, the column transistors 20a, 20b, 20b' are provided in close proximity of the bit line contacts 24a and 24b.
As best shown in FIG. 4, the conventional memory cell array is configured such that the main bit lines 30a and 30b and the main source line 32 are respectively formed on the buried local bit lines 18a and 18e and the buried local source line 18c. This means that it is not possible to narrow the pitch of the memory cell in the direction of word line (viz., in the row direction) in excess of the pitch of the main bit/source lines (viz., metal lines) 30a, 30b, and 32. In other words, in order to scale down the memory cell, it is necessary to narrow the pitch of the metal lines.